THE PIA (6532)

6.0 Address summary table

      Hex Address    Mnemonic  Purpose
      280       SWCHA     Port A; input or output  (read or write)
      281       SWACNT    Port A DDR, 0= input, 1=output
      282       SWCHB     Port B; console switches (read only)
      283       SWBCNT    Port B DDR (hardwired as input)
      284       INTIM          Timer output (read only)
      294       TIM1T          set 1 clock interval (838 nsec/interval)
      295       TIM8T          set 8 clock interval (6.7 usec/interval)
      296       TIM64T         set 64 clock interval (53.6 usec/interval)
      297       T1024T         set 1024 clock interval (858.2 usec/interval)

      NOTE: one clock is also one microprocessor machine cycle